A high-performance VLSI architecture of 2D DWT processor for JPEG2000 encoder

In this paper we present a hardware architecture of the lifting-based, two-dimensional discrete wavelet transform. The proposed architecture implements both lossless (5/3) and lossy (9/7), multi-level DWT with an embedded, symmetric extension at tile boundaries. The wavelet processor is an integral part of the hardware JPEG2000 encoder oriented for HD video applications. This article discusses optimization methods, introduced to increase design throughput up to 800 MSamples/s and solutions that rationalize the circuit area. The results of synthesis for FPGA and ASIC technology are presented.