A 10-bit 3MS/s low-power charge redistribution ADC in 180nm CMOS for neural application

This paper presents a design of low-power charge redistribution ADC implemented in UMC 180nm CMOS. The described circuit is dedicated to a neurobiological experiment. A charge sharing capacitive DAC is discussed, with a resistive sub-DAC introduced as a way of increasing resolution with small area overhead. A 40 MHz synchronous latch with preamplifier is used as a comparator. The ADC core occupies the area of 0.066 mm
²
. The simulated power consumption is 465 µW at a sample rate of 3 MS/s with DNL and INL equal to +0.21/−0.3 LSB and +1.18/−0.12 LSB respectively.