Backplane bus controller implementation in Fpga for hard real time control systems

Aircraft information management system (AIMS) requires a highly reliable backplane bus protocol for the communication between its line replaceable units (LRU) to ensure the safety critical hard real time control system operation. As the time driven protocol is more reliable than the event driven protocols, this backplane bus needs to be implemented with time division control protocol. For that matter, more attention is needed to ensure the synchronization issues between LRUs. This paper addresses the controller implementation for bus interface unit (BIU) for the ARINC 659 backplane bus as an example, which controls all the BIU operations. This controller needs to fetch the commands from the table memory, decode them and then execute them to drive the bus for the BIU operations including message operations and synchronization handling. We have designed the Instruction Set Architecture (ISA) for table commands and implemented three Finite State Machines (FSM) for designing this controller along with some glue logic. First FSM is meant for managing commands, second for managing the BIU current state for synchronization needs, and the third for controlling the BIU operations. The aforesaid design has been modeled by using Verilog, Hardware Descriptive Language (HDL) and implemented in Altera Cyclone II board. Results of Modelsim and Quartus proved the cycle accurate implementation of controller in compliance with ARINC 659 specifications.