C-V measurements of single vertical nanowire capacitors

The density of interface states, D
it
, is important for the device performance in view of the fact that it limits the inverse subthreshold slope in both, MOSFETs and TFETs [1]. This poses particular challenges for nanowire (NW) devices, because the measured D
it
is expected to increase due to the extensive processing and the various crystallographic orientations of the surface, which differ from the ideal (100) orientation. For a detailed investigation of the D
it
of NWs it is best to analyze single NW MOS capacitors. However, the capacitance of a single NW MOS capacitor lies in the fF regime which is very challenging to measure. To date, very few capacitance measurements on single NWs have been reported, e.g., on lateral devices based on InAs [2], Ge [3], and Si [4]. D
it
analysis of NWs has been demonstrated, however, based on capacitance measurements only of large arrays of InAs NWs [5]. In the present work, we report on the capacitance measurement and D
it
analysis of vertical silicon MOS capacitors based on single NWs.