Assessment of temperature dependence of the low frequency noise in unstrained and strained FinFETs

This paper aims at the studying the low frequency noise from 100 K up to room temperature in n- and p-channel triple-gate FinFET transistors with 25 nm fin-width, 65 nm fin-height, a high-k dielectric / metal gate stack, strained and unstrained substrates. These investigations allow evaluating the quality of the gate oxide interface, to identify defects in the silicon film and to make a correlation between the observed defects and some technological steps.