A 2.8 mW ΔΣ ADC with 83 dB DR and 1.92 MHz BW using FIR outer feedback and TIA-based integrator

A low-power continuous-time ΔΣ ADC for HSDPA (High-Speed Downlink Packet Access) applications provides 83 dB dynamic range and 1.92 MHz bandwidth. A high sample rate (245.76 MHz) and an FIR filter in the outer feedback path minimize susceptibility to jitter. A TIA-based integrator with direct connection of inner feedback DAC current sources to integration capacitors supports the high sample rate. The modulator, implemented using 40 nm CMOS, dissipates only 2.8 mW and achieves a 110 fJ / conversion step figure-of-merit.