A digital CDS scheme on fully column-inline TDC architecture for an APS-C format CMOS image sensor

This paper proposes a digital correlate double sampling (CDS) scheme which is suitable for a column-inline time to digital converter (TDC). The column-parallel TDCs, where measurements are made with a counter and delay line interpolation, achieve high speed A/D conversion without decreasing resolution. An APS-C format image sensor with 12-bit 360 Mpixel/s readout is realized in a cost-effective 0.18-μm CMOS technology.