A programmable MEMS-based clock generator with sub-ps jitter performance

A MEMS-based clock generator achieves sub-ps jitter in 0.18 um CMOS. Key enabling techniques include a 48 MHz MEMS oscillator, a reference doubler, a linear XOR-based PFD, a switched-resistor loop filter using accumulation mode NMOS varactors, and native NMOS devices with an RC filter. The overall output at 156.25 MHz achieves an integrated phase jitter of 668 fs rms over an integration bandwidth of 10 kHz-20 MHz.