A 2 GHz fractional-N digital PLL with 1b noise shaping ΔΣ TDC

A 2 GHz fractional-N digital PLL with a single delay cell, noise shaping ΔΣ TDC is implemented in a 0.13μm CMOS. With a simple structure of Δ modulator followed by a charge pump integrator, a wide range TDC input is converted to ΔΣ modulated bit stream. The implemented TDC consumes 1 mA, and the DPLL shows the in-band phase noise of -107 dBc at 500 kHz offset.