A 28nm poly/SiON CMOS technology for low-power SoC applications

This paper presents a state-of-the-art 28nm CMOS technology using conventional poly gate and SiON gate dielectric (Poly/SiON) with best-in-the-class transistor performance, SRAM SNM (static noise margin), MOM capacitance density and mismatch, and ULK (k=2.5) interconnect. The ION are 683 and 503 uA/um (at I
OFF
= 1nA/um, V
DD
=1V) for the n- and p-MOSFET, respectively. (With normalized t
OX
and V
DD
, these values are higher than prior publication by 5%/15%). The 6T-SRAM is aggressively scaled to <0.124um
²
with SNM of 193mV at 1.0V and 144mV at 0.7V. The via and metal resistances, and the metal-line RC time constants are competitive and well controlled. The characteristics for the RF passive components (MOM capacitor, varactor, and inductor) are also excellent.