An efficient array structure to characterize the impact of through silicon vias on FET devices

We present a test structure to measure the impact of 3D processing, especially through silicon vias, on FET devices. We also show proven techniques for enabling large numbers of devices to be accessed from a limited number of pads. We will show that through silicon via (TSV) proximity and FET channel length impact the device's behavior. We will show behavior can be predicted by symmetry. Through measurement, analsysis, and correlation with mechanical stress models, we demonstrate that our structure can predict how FET devices will behave in 3D stacked products.