An Embedded Reachability Analyzer and Invariant Checker (ERAIC)

ERAIC (Embedded Reachability Analyzer And Invariant Checker) is an essential component in our new methodology for Formal Verification of "Concrete'' Digital Circuits. We apply Model checking to a Field Programmable Gate Array (FPGA)-based prototype of the circuit[1]. At the core of ERAIC is the process of state expansion of the reachability analysis in Hardware. We aimed at a universal core expander with a Wishbone compatible structure. Its mechanism relies on full state controllability and observability offering more performance, flexibility, portability, and furthermore, the possibility of checking invariants on the Implementation Under Test (IUT) before submitting it to the model checker.