Silicon Nanowire Tunnel FETs: Low-Temperature Operation and Influence of High- $k$ Gate Dielectric

In this paper, we demonstrate p-channel tunnel FETs based on silicon nanowires grown with an in situ p-i-n doping profile. The tunnel FETs were fabricated with three different gate dielectrics, SiO
₂
, Al
₂
O
₃
, and HfO
₂
, and show a performance enhancement when using high-
k
dielectric materials. The best performance is achieved for the devices using HfO
₂
as the gate dielectric, which reach an
I
_on
of 0.1 μA/μm (
V
_DS
= -0.5 V,
V
_GS
= -2 V), combined with an average inverse subthreshold slope (SS) of ~ 120 mV/dec and an
I
_on
/
I
_off
ratio of around 10
⁶
. For the tunnel FETs with Al
₂
O
₃
as the gate dielectric, different annealing steps were evaluated, and an activation anneal at only 700°C was found to yield the best results. Furthermore, we also investigated the temperature behavior of the tunnel FETs. Ideal tunnel FET behavior was observed for devices having ohmic Ni/Au contacts, and we demonstrate the invariance of both the SS and on-current with temperature, as expected for true tunnel FETs.