The impact of transistor sizing on power efficiency in submicron CMOS circuits

Transistor size optimization is one method to reduce the power dissipation of CMOS very large scale integration (VLSI) circuits. Analysis shows that parasitic capacitances and velocity saturation of submicron technologies favor wider than minimum transistor sizes. The reason is that they allow for a larger reduction of the supply voltage which results in more substantial power savings. SPICE simulation of prescalers with differently scaled transistors confirm the analysis. The same prescaler has been implemented in a 1.0-/spl mu/m CMOS technology with minimum sized transistors and with optimized transistors for high speed. Measurements confirm that power dissipation is reduced for optimized transistor sizes.