Low power design of RFID tags

Low-power design is essential for passive RFID tags to achieve expected level of sensitivity. Considering the mechanism of the passive tags powered, a low peak power is also important. This paper is focused on optimization on peak power. A tag IC is also presented. The IC, which is compatible with the EPC C1G2 RFID protocol, was designed and fabricated successfully by using a 0.18μm process, with a tested sensitivity of -16dBm.