FPGA Based High Speed BCH Encoder for Wireless Communication Applications

This paper presents prototyping of a high speed and area efficient BCH encoder on an FPGA target device for wireless communication applications. FPGA implementation is very fast, easy to modify and suitable for prototyping products. BCH encoder is usually implemented with linear feedback shift register architecture. BCH codes can be defined by two parameters that are numbers of errors to be corrected and code size. The proposed BCH encoder has been developed and simulated using Matlab along with Xilinx DSP Tools, synthesized with XST and implemented on Spartan 3E target FPGA device. The results show that proposed BCH encoder can operate at a maximum frequency of 249.8 MHz by consuming negligible resources of target device.