Comparative Analysis of Low Power Multiplier Architectures

This paper presents a comparative analysis of four different multiplier architectures. The four multipliers include the array multiplier, a bypass multiplier with tree structure, a multiplier with 2-d bypass, and a bypass multiplier using improved column bypassing schemes. The multipliers a reimplemented in 90nm CMOS technology. The architectures are compared in terms of critical path delay, power dissipation and area in terms of transistor count. The multipliers perform worse compared to the array multiplier in terms of power due to the scaling effects on leakage current. Each of the three multipliers has its own trade-offs between power and delay.