Design of JPEG2000 Arithmetic Coder Using Optimized Renormalization Procedure

JPEG2000 of high performance is one of the best solutions for video transmission in the wireless environment with features of multi-hop and low data rate. Arithmetic coder is used for entropy coding in JPEG2000, which involves heavy loop-iterative operations, restricting the performance of the whole JPEG2000 encoder. In this letter, an efficient algorithm for the renormalization procedure is present, which enables the whole arithmetic coder to perform sequentially, reducing the computation and easy to implement on hardware. The hardware architecture is present, reading in and encoding one pair of CX/D per cycle. The experimental results on FPGA are present. The clock rate can be synthesized into 79.836MHz, and the system throughout is 79.836 Msymbols/s.