Low power and fast adder implementation with Double Gate MOSFETs

In this paper we present implementation of a 32-bit adder using Quad Carry Look Ahead(QCLA) algorithm in compound domino logic with Merged Pre-charge Keeper transistor and Statistically Skewed Inverter with Double Gate MOSFET(DGMOSFET)s. The worst case propagation delay of the adder is 220ps. The average operating power is 186 µW.