Neural networks in CMOS: a case study

The design of a six-neuron chip using 1.3- mu m CMOS gate-array technology is described. With these neuro-chips, the authors developed a general-purpose neural-network system that can simulate a wide range of neural networks, including Hopfield-type networks, back propagation networks, and many others. The system consists of several neuro-boards and a host computer. Each neuro-board contains 72 neuro-chips, which constitute a network of 54 neurons with 2916 excitatory and 2916 inhibitory synapses. The computer can read and write various registers in the neuro-board, learning algorithms can be executed, and synaptic strength can be easily updated. A hierarchical bus structure of time-sharing buses connects each of the neurons on the wafer. As fabricated, the neuro-WSI uses 0.8- mu m, three-level-metal CMOS gate-array technology.<
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