Efficient design for transistor level and function

This paper proposes a new design of 2T AND gate. All the designs are compared with respect to the transistor count, power consumption, temperature sustain ability, noise immunity and parasitic capacitance in order to prove the superiority of proposed design over existing designs. The pre layout simulation has been carried out on BSIM3v3 90nm technology and post layout simulation has been performed on 0.5 submicron technology using Tanner EDA tool.