Static power reduction utilizing data dependency in MBFA topologies

In this paper, we discusses the concept of data dependency in Majority Based Full Adder (MBFA) topologies. MBFA topologies promise better area requirements over the conventional adders as the number of transistors are reduced. Use of single Vt transistors for the realization of these adders leads to increase in power consumption when compared to other topologies, but taking the dependency of power consumption on incoming data stream in to consideration a significant improvement in power requirement can be achieved. Two addressing schemes are proposed to help in improvement of power consumption of MBFA to half values, when used in address calculation. The adders are studied in 180 nm CMOS process technology using a supply voltage of 1.8 V.