Impact of gate engineering on double gate MOSFETs using high-k dielectrics

This paper analyses the impact of gate engineering on the performance of MOSFETs for system-on-chip applications with high K dielectrics. The performance is analysed for parameters such as electrostatic surface potential, transconductance using a 2D device simulator ISE TCAD. Equivalent Oxide Thickness (EOT) of gate oxide can be reduced by the usage of high K dielectric materials. The gate engineering technique used here is the dual metal gate technology Due to their excellent scalability and better immunity to short channel effects, dual material double-gate (DM DG) MOSFETs are being easily assessed for CMOS applications beyond the 70 nm of the SIA roadmap 2008. Gate engineered devices show an improvement in the analog performance for different high k dielectrics. The gate engineered device show an increase of drain current by about 5% in the subthreshold region and a 3% increase in transconductance in strong inversion. For analog applications, importance is given to the subthreshold regime as CMOS circuits operated in this regime are very much attractive for ultralow-power high-gain performances.