Carbon-based Schottky barrier transistor: From compact modeling to digital circuit applications

This paper presents a comprehensive approach starting from compact model development for the Schottky barrier carbon nanotube field effect transistor (SB-CNTFET) to digital circuit simulation. The present compact model is essentially based on a novel formulation of the channel density of charge (Q
_cnt
). This Q
_cnt
is solved analytically using approximations for the transmission function T(E). Then, the compact model is used to simulate basic logical inverter gate. Thus, the influence of the Schottky barrier features (SB) on the voltage transfer characteristic (VTC) has been highlighted. Six transistor static memory cell (6T-SRAM) is presented and simulated on either read and write operations. Finally, for the assessment of the SB on the 6T-SRAM performances, transient power consumption results are compared with those of the conventional CNTFET with zero-SB height.