250Mb/s to 3Gb/s unilateral continuous rate CDR using precise frequency detector and 1/5-rate linear phase detector

This paper describes a 250-Mb/s to 3Gb/s continuous rate clock and data recovery (CDR) circuit in the TSMC 90nm CMOS process. The circuit first recovers the precise clock frequency from bit-serial 2
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-1 pseudorandom binary-sequences (PRBS) across a wide range of data rates. Thus, the requirements for loop bandwidth and locking range is much relaxed for the second step of phase detection, implemented as a 1/5 rate linear phase detector (PD) offering reduced clock operating frequency and low jitter. The CDR achieves 12.6-ps peak-to-peak jitter at 2.5Gb/s and consumes a current of 3.84mA in post-layout simulation.