Architecture of a 50 MFIPS fuzzy processor and the related 1 /spl mu/m VLSI CMOS digital circuits

This paper deals with two problems: the first concerns the design of the HW architecture of a high speed fuzzy processor that can work at 50 Mega fuzzy inference per second (MFIPS). It has eight 7 bit inputs and one 7 bit output. It is foreseen to apply it to a trigger device in HEP (High Energy Physics) experiments, the second one concerns the 1 /spl mu/m CMOS VLSI design of the fuzzification and inference process, the MIN-MAX and the defuzzifier circuits, using the ES2 standard cells, which work with a delay less than 20 ns. These circuits have already been realized and tested. The design has been done using Cadence tools we got from Eurochip. At present a 4 input fuzzy processor has been fully designed and it has been recently sent to ES2 to be realized. Fuzzy processors that run at this speed are not available on the market and this is the innovative feature of this design.