Performance-driven interconnection allocation

This paper addresses the problem of performance-driven interconnection synthesis in a bus based VLSI architecture. We present the inter-dependence problem between interconnection allocation and floorplanning, and we give a new approach to interconnection synthesis based on a two step technique. The first step consists of communication-oriented floorplanning, which places components at architectural level while minimising the communications cost. The second step consists of assigning communications to interconnections. It minimises the propagation delay by balancing the loads on the interconnections and reducing their estimated lengths.