A multirate double-sampling sigma delta modulator for multi-standard wireless radio receivers

A novel multirate double-sampling sigma delta modulator is proposed for the low power A/D converter for multi-standard wireless applications. A cascade 2-2 structure is designed for the modulator. The multirate technique reduces the sampling rate of the 1
^st
stage integrator to relax the performance requirements of the operational amplifiers(OPAMP), which in turn results in low power consumption. The double-sampling technique is adopted to update the integrator output of the switched capacitor circuit during the both clock phases of the master clock. The sampling frequency is twice of the master clock frequency. The clock frequency can be halved to relax the settling time of the OPAMPs to achieve the similar performance concerning the signal to noise ratio with the conventional sigma delta modulator, which decreases the power dissipation. In comparison with the conventional double-sampling sigma delta modulator topology, the proposed modulator architecture obtains the similar performance with a low slewrate requirement of the 1
^st
stage integrator. The power dissipation is effectively decreased.