Implementation of fast Hartley transform on multiple bus cache coherent multiprocessors

The use of multiple bus as interconnection network for multiprocessors has shown attractive features as compared to the existing ones. The addition of cache memory makes the architecture still a high performance one. In this paper we consider the implementation of Hou's FHT on multiple bus cache coherent multiprocessors. The analytical formulas are developed and performances are analysed in terms of speedup using these formulas. We also study the limitations of the inter processor communication overhead and propose a modification to the signal flow graph in order to minimise the multiprocessor execution time and hence to improve the speedup performance of the system.