3D interconnection using butterfly via for high speed and RF package design

Semiconductor markets require continuous device miniaturization while the I/O density and the frequency/speed of operation increase. Maintaining acceptable signal integrity at the system level has become more challenging than ever. Impedance control at high speeds of operation is one of the key elements of good signal integrity design. Impedance is relatively easy to control for 2D transmission lines, however becomes quite challenging for 3D structures such as wirebond's or vias. It is generally accepted that the silicone package is a major design challenge in obtaining good system level performance. In this paper, a butterfly (fan-shape) via structure is proposed for impedance control and improved shielding. Our proposed via structure is 60% ~ 80% smaller compared to a typical through hole via therefore enables real estate saving at the package level as well.