Evaluation of h/sub FE/ fluctuation of high-performance IDP emitter transistors by using test structures

Current gain (h/sub FE/) fluctuation of in-situ phosphorus doped polysilicon (IDP) emitter transistors has been analyzed using a new test structure. From the electrical data, it has been revealed that there are some transistors with low h/sub FE/ at random distribution in a wafer and also in a chip. Further experiments and TEM analysis show the phenomenon is mainly due to the interfacial condition between emitter poly-Si and mono-Si.