Measurement and characterization of multi-layered interconnect capacitance for deep submicron VLSI technology

This paper presents the measurement and characterization of multi-layered interconnect capacitances for a 0.35 /spl mu/m CMOS logic technology, which is becoming a critical circuit limitation to high performance VLSI design. To measure multi-layered capacitances of interconnect lines, test structures and the measurement methodology are presented. The measured interconnect capacitances were employed to evaluate and calibrate TCAD tools for the simulation of high-speed interconnect technologies.