Experimental results from a pixel front-end for the NA62 experiment with on pixel constant fraction discriminator and 100 ps Time to Digital Converter

The paper presents test results of a front-end ASIC developed for fast timing applications with silicon pixel detectors. Implemented in a 0.13 μm CMOS process, the prototype integrates 107 read-out cells. In an area of 300 μm × 300 μm each cell incorporates a fast transimpedance amplifier with 3 ns peaking time, a Constant Fraction Discriminator (CFD) and a Time to Digital Converter (TDC). The analog front-end is optimized for signals from 1 fC to 10 fC and dissipates lmW from a 1.2 V supply. Electrical tests of the key building blocks and system level aspects are discussed in the paper.