Observation and Effective Suppression of Dielectric Relaxation in Charge-Trap NAND Flash Memory

We measured instant VΛ change coming from the relaxation effect in high-k dielectric layer in CTF. A counter-pulse scheme was proposed to solve the issue in CTF memory, by inserting short positive gate pulse between erase execution pulse and verify read step, whose validity was confirmed in our NAND test vehicle main cell array.