A systematic study of I/O device designs for TSV-based 3D chip stacking

A systematic study of I/O device designs for TSV 3D chip stacking is reported. For the primary ESD circuit using SCR, a twin well structure results in minimal transient overshoot current and voltage while its triggering voltage is higher than in Deep N-well (DNW) structures. For nMOSFET-based secondary ESD circuit components, the DNW should be applied to handle the current overshoot and the design rule should be further scaled.