A CAD compatible SOI/CMOS gate array having body-fixed partially-depleted transistors

This 0.35/spl mu/m 220kG SOI/CMOS gate array uses partially-depleted devices and allows use of cell libraries and design methods compatible with bulk/CMOS gate arrays by optimizing the basic-cell layout and power-line wiring. The SOI/CMOS gate array operates at 2.0V consuming 65% less power than typical 0.35/spl mu/m 3.3V bulk/CMOS gate arrays.