Comparative design methodologies for FPGA based computer arithmetic

Digital systems are growing in size at an exponential rate. This growth is causing the systems to quickly become less comprehendable to the human mind. Many CAD tools have been developed in the past to deal with the increased complexity of these systems. Although many of these tools are helpful and still widely used, the most promising and quickly advancing technology for digital design is the VHDL language. The use of the VHDL language and logic synthesis tools to implement complex systems is increasing rapidly. The focus of this research is to compare two design environments used for VHDL design and synthesis. The two environments are the Altera Max+PLUS II design environment and the Viewlogic Workview Office design environment. A qualitative comparison is made between the two design environments as they are used by the designer. Also, a quantitative analysis is made using a floating point arithmetic unit to compare the VHDL synthesis results of these two design tools.