An architecture based on the memory mapped node addressing in reconfigurable interconnection network

The paper proposes an architecture for a scalable supercomputing machine, based on a distributed virtual shared memory system. The processing elements used in this system consist of an ASIC embedding 5 PEs, 20 floating point multipliers, 15 adders, and one divider and square root arithmetic unit in a single chip. The 5 PEs are interconnected with a complete graph. The reconfigurable architecture is designed for dynamic high performance applications like virtual reality or multimedia systems. One chip implements a cluster, and an intercluster network can be established through a multiple interconnection network of these chips. It has 3.0 Gflops/chip as hardware peak performance, and can be scaled by an optical link via a specified router.