Methodologies for efficient asynchronous circuits design

This paper describes the approaches for transistor count minimization for asynchronous control modules. In this design, pull-up/pull-down CMOS is used to implement asynchronous (or self-timed) circuits, which are 4-phase handshake rind dual-rail data format. One of the control blocks, IF module, is discussed as an application example. Moreover, the comparison of transistor count between new implementation and conventional design is included. The functional verification is done by SPICE simulation.