Reconfigural content addressable memory for ASIC module compiler

This paper discusses the content addressable memory (CAM) architecture for ASIC module compiler. CAM is used to perform parallel search, data search using inexact match capability, and logical operation, but a new and easy design method is required to adopt CAM in ASIC design. To generate CAMs of various architectures, research on the CAM architecture is performed. As a result, reconfigurable leaf cells and flexible floor-plan for 0.6 /spl mu/m TLM CMOS are obtained.