Vector-radix IDCT implementation for MPEG decoding

This paper introduces a hardware architecture and VHDL implementation of a Vector-Radix DCT/IDCT algorithm. The architecture provides a true generic structure for both DCT and IDCT. For MPEG-1 video IDCT, it can run at a low frequency of 27 MHz to meet the data rate at SIF resolution with the additional capability of handling part of an inverse quantization task. For MPEG-2 at MP@ML, the IDCT can be carried out at 81 MHz clock rate. The 8/spl times/8 implementation can also be easily upgraded to handle any N/spl times/N transform of power of two.