Clock tree distribution

The semiconductor industry is moving toward submicron and deep submicron (0.5 μm and below) technologies. As the chip size keeps decreasing, the chip capacity keeps increasing. New challenges are appearing on high speed ASIC (Application Specified Integrated Circuit) design. Building a balanced clock tree is now essential for the success of any advanced VLSI (Very Large Scale Integration) design. The interconnect wire delay is as important as the logic gate delay.