A Novel mechanism for speed characterization during delay test

The impact of di/dt noise and static IR drop on at-speed scan testing has been reported in literature. Delays of paths can be impacted during delay testing by IR drop and di/dt noise in ways that change the delay ordering of paths. This, in turn, affects the ability of such tests to catch certain delay defects and impairs its use for speed binning. It is important, therefore, to address IR drop during delay tests. This paper proposes an instrumentation methodology for a design based on launch-off-capture delay tests to control the time interval between shift and capture cycles. This mechanism improves speed characterization of devices and achieves a higher capture frequency compared with traditional methods. It also addresses reduction of di/dt noise during capture. The proposed scheme is realized by (i) pipelined scan-enable and (ii) a deterministic launch-and-capture method for the tile under test. This mechanism has been implemented on silicon and experimentally observed to increase the speed of a device between 8% and 24% relative to traditional methods.