An H.264 full HD 60i double speed encoder IP supporting both MBAFF and Field-Pic structure

HD video sequences are widely used in today's multimedia systems and many of these are encoded with H.264 codec. However, it is still challenging to develop a high-performance H.264 encoder because the H.264 encoding process needs a large amount of computations and memory accesses. In this paper, a novel H.264 encoder is described. This encoder can encode video sequences of full HD 60i at double speed. Both MBAFF and Field-Pic structure are supported as coding tool for interlaced video sequences. The memory bandwidths are reduced by using a hierarchical motion estimation method and a pipeline configuration with consideration of MBAFF. The encoder is implemented with 1637 K logic gates and 336.5 KB on-chip SRAM in the 65 nm CMOS technology.