Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

Since target applications in embedded systems are limited, we can optimize its cache configuration. A very fast and exact cache simulation algorithm, CRCB, has been recently proposed. CRCB assumes LRU as a cache replacement policy but FIFO- or PLRU-based cache is often used due to its low hardware cost. This paper proposes exact and fast L1 cache simulation algorithms for PLRU- or FIFO-based caches. First, we prove that CRCB can be applied to FIFO and PLRU. Next, we show several properties for FIFO- and PLRU-based caches and propose their associated cache-simulation speed-up algorithms. Experiments demonstrate that our algorithms run up to 300 times faster than a well-known cache simulator.