Hierarchical trigger generation for post-silicon debugging

The post-silicon debugging process is aimed at locating design errors and electrical errors that concealed themselves during the whole process of pre-silicon verification. Although during post-silicon validation engineers can exploit the high speed of hardware prototype to exercise huge amount of test vectors, low level of real-time observability and controllability of signals inside the prototype is too big an issue for them. Various DFD techniques have come to improve observability of signals and expedite root cause analysis. Recently, typical practical DFD approaches are based on the Embedded Logic Analysis ELA. Since ELA has limitation in terms of the amount of data that can acquire in a debug experiment, we have to either increase the size of trace buffer or try to use trigger unit that can effectively control when to acquire the debug data. In this paper, we propose ZiMH a trigger generator that builds trigger unit. Additionally, it provides resourceful trace information for root cause analysis. Major advantages of generated trigger unit over traditional trigger units are: 1) it facilitates failure localization and root-cause analysis by keeping the trace of interaction that leads to the failure 2) it can be tuned for specific location to avoid the huge cost related to interfacing with trace signals 3) it can get parameterized to generate several trigger units that can be placed inside the limited area.