SAT for heterogeneous FPGA technology mapping

Modern FPGAs employ heterogeneous architecture to reduce power dissipation, area overhead, and to improve performance. Besides lookup tables, heterogeneous FPGA also contains ASIC-like sub-circuits and macro-gates. If a programmable logic block with n inputs contains macro-gates, a Boolean function with n variable may not be implemented in it. In this paper, a Boolean satisfiability based technology mapping methods is suggested, which us symmetry to speed up the mapping process.