A LDO regulator with slew-rate enhancement circuit for low-power SoC

A low dropout (LDO) regulator is designed in this paper. By adopting a slew rate enhancement circuit, the slew rate of the LDO output is obviously improved when the load current is suddenly switched from low to high. Moreover, employing a simple bias circuit, the architecture of the LDO regulator is simple, and can be fabricated by conventional CMOS technology. The LDO regulator is designed and simulated in CSMC 0.5μm CMOS process. Simulation results show that the PSRR of the LDO regulator at 100Hz, 1kHz and 10kHz achieves, respectively, -76dB, -70dB and -52dB at room temperature and V
_dd
=2V. The circuit can provide an output voltage of 1.2V with a variation of 8mV in a load current range from 0 to 50mA. The deviation of the output voltage is within 11mV when power supply voltage V
_dd
changes from 1.4V to 6V.