A 0.1–2 GHz CMOS RF front-end for Software-Defined Radio applications

In this paper, A Software-Defined Radio (SDR) RF front-end is presented that contains LNA, mixers, VGAs, and frequency synthesizer, supporting various wireless communication standards in 0.1–2 GHz while guaranteeing a power/performance trade-off at any time. The circuit is fabricated in a 0.18 µm RF CMOS technology with 1.8 V supply voltage. Simulated result shows that the receive path achieves a Noise Figure of 3.8 dB at 160 MHz and 5.5 dB at 2 GHz. The Output-referred 3rd-order Intercept Point (OIP3) is high up to 21.3 dBm at 800 MHz. The voltage gain of the front-end is between 16–44 dB. The phase mismatch of LO quadrature signals is lower than 3°. It consumes 78.8 mW at the 1.8V supply.