Improvement of gate critical dimension for 40nm node device

We tried to improve the variation of gate critical dimension(CD) within-wafer for 40nm node device at gate etching condition especially Bottom-Anti-Reflective-Coat (BARC) etching step. Gas diffusion influences in the etching chamber and temperature effects of electrostatic chucked (ESC) were investigated in this study. Finally it was achieved the optimal etching condition which significantly improved the within-wafer variation of the gate CD.